module lattice2
(
		input              clk          ,
		input              rstn         ,
		//input              key          ,
		
		output reg [4:0]   dig          ,
		output reg [15:0]  seg_lattice
);

parameter CNT_T60MS = 23'd3_000_00;

reg [22:0] count;
reg        flag1;
reg [15:0] m;
reg        clk_out;
reg [4:0]static_cnt0;
reg [4:0]static_cnt1;
reg [4:0]static_cnt2;
reg [4:0]static_cnt3;
reg [4:0]static_cnt4;
reg [4:0]static_cnt5; 
reg [4:0]static_cnt6;
reg [4:0]static_cnt7;
reg [4:0]static_cnt8;
reg [4:0]static_cnt9;
reg [4:0]static_cnt10;
reg [4:0]static_cnt11; 
reg [4:0]static_cnt12;
reg [4:0]static_cnt13;
reg [4:0]static_cnt14;
reg [4:0]static_cnt15;

//动态扫描
always@(posedge clk or negedge rstn)
begin
       if(!rstn) begin 
		   m <= 1'b0;
			clk_out <= 1'b0;
			end 
		 else begin 
		     m <= m + 1'b1;
			  if(m == 24999)
			     clk_out <= ~clk_out;
			  if(m == 49999)begin 
			           m <= 0;
			     clk_out <= ~clk_out;
			   end 
		 end 
end 
//4-16片选译码
always@(posedge clk_out or negedge rstn)begin
        if(!rstn)
		     dig <= 5'd0;
		  else if(dig == 5'd31)
		     dig <= 5'd0;
		  else 
		     dig <= dig + 1'b1;
end 
//数值变换计数器，标志位
always@(posedge clk or negedge rstn) begin  
        if(!rstn) begin 
		     count <= 23'd0;
			  flag1 <= 1'b0;
		  end 
		  else if(count == CNT_T60MS)begin
		     count <= 23'd0;
			  flag1 <= 1'b1;
		  end 
		  else begin 
		     count <= count + 1'b1;
			  flag1 <= 1'b0;
		  end 
end 

reg [22:0] n;
reg        clk_out1;
reg [3:0]  state;
//数值变换分频
always@(posedge clk or negedge rstn)begin
       if(!rstn) begin 
		   n <= 1'b0;
			clk_out1 <= 1'b0;
			end 
		 else begin 
		     n <= n + 1'b1;
			  if(n == 149999)
			    begin 
					clk_out1 <= ~clk_out1;
				   n <= 0;
				 end 
			
		 end 
end 
//状态机
always@(posedge clk_out1 or negedge rstn)begin
       if(!rstn)
		   state <= 4'd0;
		 else if(state == 4'd15)begin 
         state <= 4'd0; end 
		 else 
		   state <= state + 1'b1;
end 

always@(posedge clk or negedge rstn)begin
        if(!rstn) begin 
		    static_cnt0 <= 5'd0;
			 static_cnt1 <= 5'd1;
			 static_cnt2 <= 5'd2;
			 static_cnt3 <= 5'd3;
			 static_cnt4 <= 5'd4;
			 static_cnt5 <= 5'd5;
			 static_cnt6 <= 5'd6;
			 static_cnt7 <= 5'd7;
			 static_cnt8 <= 5'd8;
			 static_cnt9 <= 5'd9;
			 static_cnt10 <= 5'd10;
			 static_cnt11 <= 5'd11;
			 static_cnt12 <= 5'd12;
			 static_cnt13 <= 5'd13;
			 static_cnt14 <= 5'd14;
			 static_cnt15 <= 5'd15;
		
		  end 
		  else begin 
		  case(state)
					 4'd0: begin
					       if(flag1)
							 static_cnt0<=static_cnt0+1'b1;
							 else
							 static_cnt0<=static_cnt0;
                      end 
                4'd1: begin
					       if(flag1)
							 static_cnt1<=static_cnt1+1'b1;
							 else
							 static_cnt1<=static_cnt1;
                      end 
                4'd2: begin
					       if(flag1)
							 static_cnt2<=static_cnt2+1'b1;
							 else
							 static_cnt2<=static_cnt2;
                      end 
                4'd3: begin
					       if(flag1)
							 static_cnt3<=static_cnt3+1'b1;
							 else
							 static_cnt3<=static_cnt3;
                      end 
                4'd4: begin
					       if(flag1)
							 static_cnt4<=static_cnt4+1'b1;
							 else
							 static_cnt4<=static_cnt4;
                      end 
                4'd5: begin
					       if(flag1)
							 static_cnt5<=static_cnt5+1'b1;
							 else
							 static_cnt5<=static_cnt5;
                      end 
                4'd6: begin
					      if(flag1)
							 static_cnt6<=static_cnt6+1'b1;
							 else
							 static_cnt6<=static_cnt6;
                      end 
                4'd7: begin
					       if(flag1)
							 static_cnt7<=static_cnt7+1'b1;
							 else
							 static_cnt7<=static_cnt7;
                      end 
                4'd8: begin
					       if(flag1)
							 static_cnt8<=static_cnt8+1'b1;
							 else
							 static_cnt8<=static_cnt8;
                      end 
                4'd9: begin
					       if(flag1)
							 static_cnt9<=static_cnt9+1'b1;
							 else
							 static_cnt9<=static_cnt9;
                      end 
                4'd10: begin
					       if(flag1)
							 static_cnt10<=static_cnt10+1'b1;
							 else
							 static_cnt10<=static_cnt10;
                      end 
                4'd11: begin
					       if(flag1)
							 static_cnt11<=static_cnt11+1'b1;
							 else
							 static_cnt11<=static_cnt11;
                      end 
                4'd12: begin
					       if(flag1)
							 static_cnt12<=static_cnt12+1'b1;
							 else
							 static_cnt12<=static_cnt12;
                      end 
                4'd13: begin
					       if(flag1)
							 static_cnt13<=static_cnt13+1'b1;
							 else
							 static_cnt13<=static_cnt13;
                      end 

                4'd14: begin
					       if(flag1)
							 static_cnt14<=static_cnt14+1'b1;
							 else
							 static_cnt14<=static_cnt14;
                      end 

                4'd15: begin
					       if(flag1)begin
							 static_cnt15<=static_cnt15+1'b1; end
							 else
							 static_cnt15<=static_cnt15; 
                      end 
					 endcase
							 
           end 

end 

reg [4:0] num_drip;

always@(posedge clk or negedge rstn)begin
        if(!rstn) 
				num_drip <= 5'd0; 
			else begin 
		    case(dig)
			      4'd0:  num_drip <= static_cnt0;
					4'd1:  num_drip <= static_cnt1;
					4'd2:  num_drip <= static_cnt2;
					4'd3:  num_drip <= static_cnt3;
					4'd4:  num_drip <= static_cnt4;
					4'd5:  num_drip <= static_cnt5;
					4'd6:  num_drip <= static_cnt6;
					4'd7:  num_drip <= static_cnt7;
               4'd8:  num_drip <= static_cnt8;
					4'd9:  num_drip <= static_cnt9; 
					4'd10: num_drip <= static_cnt10;
					4'd11: num_drip <= static_cnt11;
               4'd12: num_drip <= static_cnt12;
					4'd13: num_drip <= static_cnt13;
					4'd14: num_drip <= static_cnt14;
					4'd15: num_drip <= static_cnt15;
					4'd16:  num_drip <= static_cnt0;
					4'd17:  num_drip <= static_cnt1;
					4'd18:  num_drip <= static_cnt2;
					4'd19:  num_drip <= static_cnt3;
					4'd20:  num_drip <= static_cnt4;
					4'd21:  num_drip <= static_cnt5;
					4'd22:  num_drip <= static_cnt6;
					4'd23:  num_drip <= static_cnt7;
               4'd24:  num_drip <= static_cnt8;
					4'd25:  num_drip <= static_cnt9;
					4'd26: num_drip <= static_cnt10;
					4'd27: num_drip <= static_cnt11;
               4'd28: num_drip <= static_cnt12;
					4'd29: num_drip <= static_cnt13;
					4'd30: num_drip <= static_cnt14;
					4'd31: num_drip <= static_cnt15;
					endcase
					
			end 
			
end 

always@(posedge clk or negedge rstn)
begin 
      if(!rstn)
		   seg_lattice <= 16'd0;
		else 
	       begin 
			 case(num_drip)
			      4'd0:  seg_lattice <= 16'b1111_1111_1111_1111;
					4'd1:  seg_lattice <= 16'b1101_1111_1111_1111;
					4'd2:  seg_lattice <= 16'b1101_1111_1111_1111;
					4'd3:  seg_lattice <= 16'b1101_1111_1111_1011;
					4'd4:  seg_lattice <= 16'b1101_1111_1111_1011;
					4'd5:  seg_lattice <= 16'b1101_1111_1111_1011;
					4'd6:  seg_lattice <= 16'b1101_1111_1111_1011;
					4'd7:  seg_lattice <= 16'b1100_0000_0000_0011;
               4'd8:  seg_lattice <= 16'b1100_0000_0000_0011;
					4'd9:  seg_lattice <= 16'b1101_1111_1111_1011;
					4'd10: seg_lattice <= 16'b1101_1111_1111_1011;
					4'd11: seg_lattice <= 16'b1101_1111_1111_1011;
               4'd12: seg_lattice <= 16'b1101_1111_1111_1011;
					4'd13: seg_lattice <= 16'b1101_1111_1111_1111;
					4'd14: seg_lattice <= 16'b1101_1111_1111_1111;
					4'd15: seg_lattice <= 16'b1111_1111_1111_1111;
			      4'd16: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd17: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd18: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd19: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd20: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd21: seg_lattice <= 16'b1101_1111_1111_1111;
					4'd22: seg_lattice <= 16'b1101_1111_1111_1111;
					4'd23: seg_lattice <= 16'b1111_1111_1111_1111;
               4'd24: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd25: seg_lattice <= 16'b1111_1111_1011_1111;
					4'd26: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd27: seg_lattice <= 16'b1111_1111_1111_1111;
               4'd28: seg_lattice <= 16'b1111_1111_1101_1111;
					4'd29: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd30: seg_lattice <= 16'b1111_1111_1111_1111;
					4'd31: seg_lattice <= 16'b1111_1111_1111_1111;
          endcase
			end
end 

endmodule 
